Power Supply Design Tips: Beware of SEPIC Coupled Inductor Loop Currents – Part 1

In this Power Supply Design Tips, we will identify some leakage inductance requirements for coupled inductors in SEPIC topologies. SEPIC is a very useful topology when electrical isolation between primary and secondary circuits is not required and the input voltage is either higher or lower than the output voltage. We can use it in place of a boost converter when short circuit protection is required.

By Robert Kollman, Texas Instruments (TI)

In this Power Supply Design Tips, we will identify some leakage inductance requirements for coupled inductors in SEPIC topologies. SEPIC is a very useful topology when electrical isolation between primary and secondary circuits is not required and the input voltage is either higher or lower than the output voltage. We can use it in place of a boost converter when short circuit protection is required. SEPIC converters feature single-switch operation and continuous input current, resulting in low electromagnetic interference (EMI). This topology (shown in Figure 1) can use two separate inductors (or since the inductors have similar voltage waveforms), and therefore a coupled Inductor, as shown. Coupled inductors are attractive because they are smaller in size and cost than two separate inductors. The disadvantage is that standard inductors are not always optimized for all possible applications.

Power Supply Design Tips: Beware of SEPIC Coupled Inductor Loop Currents – Part 1
Figure 1 SEPIC converter uses a switch to ramp up and down the output voltage

The current and voltage waveforms of this circuit are similar to continuous current mode (CCM) inverting circuits. When Q1 is turned on, it uses the input voltage of the coupled inductor main stage to form energy in the circuit. When Q1 is turned off, the voltage across the inductor is reversed and then clamped to the output voltage. Capacitor C_AC is what differentiates the SEPIC from the inverse circuit; when Q1 is on, the secondary inductor current flows through it and then goes to ground. When Q1 is off, the primary inductor current flows through C_AC, increasing the output current through D1. A big benefit of this topology over an inverting circuit is that both the FET and diode voltages are clamped by C_AC and there is very little ringing in the circuit. In this way, we can choose to use lower voltages, and thus produce higher power efficiency devices.

Since this topology is similar to the inverse topology, many would argue that a tightly coupled set of windings is required. However, this is not the case. Figure 2 shows two operating states of a continuous SEPIC whose transformer has been modeled by leakage inductance (LL), magnetizing inductance (LM), and an ideal transformer (T). Upon inspection, the voltage of the leakage inductance is equal to the voltage of C_AC. Therefore, a large AC voltage with a small value of C_AC or a small leakage inductance results in a large loop current. Larger loop currents degrade converter efficiency and EMI performance, which is undesirable. One way to reduce this large loop current is to increase the coupling capacitor (C_AC). However, doing so comes at the cost of cost, size and reliability. A more astute approach is to increase the leakage inductance, which can be easily achieved by specifying a custom magnetic assembly.

Power Supply Design Tips: Beware of SEPIC Coupled Inductor Loop Currents – Part 1
2a) MOSFET on: VLL = VC_AC – VIN = ∆VC_AC(DC part removed)

Power Supply Design Tips: Beware of SEPIC Coupled Inductor Loop Currents – Part 1
2b) MOSFET off: VLL = VIN + VOUT – VC_AC – VOUT = ΔVC_AC (DC part removed)
Figures 2a and 2b Two operating states of the SEPIC converter.

The AC voltage of the leakage inductance is equal to the coupling capacitor voltage.

Interestingly, very few manufacturers have recognized this fact and many have produced inductors with low leakage inductance for SEPIC applications. Coilcraft, on the other hand, has a 47 uH MSD1260 with about 0.5 uH leakage inductance, and has recently developed other versions of this design with more than 10 uH leakage inductance, which we will cover in our next Power Supply Design Tips “Introduction to it, so stay tuned.

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“In this Power Supply Design Tips, we will identify some leakage inductance requirements for coupled inductors in SEPIC topologies. SEPIC is a very useful topology when electrical isolation between primary and secondary circuits is not required and the input voltage is either higher or lower than the output voltage. We can use it in place…